D. Jang, J. Kim, U. Lee, J. Suh, and W. Jung, “Techniques for Analyzing and Reducing Voltage Conversion Ratio Transition Losses of Capacitive DC–DC Converters for Fast-DVS-Enabled Systems”, IEEE Transactions on Power Electronics (TPEL), Oct. 2021.
H. Shin, J. Kim, D. Jang, D. Cho, Y. Jung, H. Cho, U. Lee, C. Kim, S. Ha, and M. Je, “An Energy-Efficient Three-Stage Amplifier Achieving a High Unity-Gain Bandwidth for Large Capacitive Loads Without Using a Compensation Zero”, IEEE Solid-State Circuits Letters (SSCL), Nov. 2020.
D. Jang, J. Kim, and W. Jung, “A Fully Integrated Fine-Grained Dual-Output Switched-Capacitor DC-DC Converter for Low-Power Applications”, IDEC Journal of Integrated Circuits and Systems (JICAS), Jul. 2021.
🎤 Conferences
D. Jang, D. Ko, D.W. Kim, J. Kim, B. Moon, and W. Jung, “A Single/Dual-Output Switched-Capacitor DC-DC Converter with Geometrically Arranged Soft VCR Transitions”, IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2024.
H.-H. Bae, J.-H. Cho, K. Kim, S. Shin, D. Jang, J.-H. Yang, and H.-S. Kimm, “A 7V/μs-DVS Class-G Digital-Shunt-Aided Buck Voltage Regulator Achieving a 7% Dynamic-Efficiency Drop at a 600kHz DVS Occurrence Frequency in 28nm CMOS”, IEEE Custom Integrated Circuits Conference (CICC), Apr. 2024.
H. Shin, D. Jang, G.-G. Kang, J. Kim, C. Kim, S. Ha, and M. Je, “A 96.6%-Efficiency Continuous-Input-Current Hybrid Dual-Path Buck-Boost Converter with Single-Mode Operation and Non-Stopping Output Current Delivery”, IEEE Symposium on VLSI Circuits (SOVC), Jun. 2021.
D. Jang, U. Lee, J. Kim, J. Suh, and W. Jung, “An On-Chip Dual-Output Switched-Capacitor DC- DC Converter with Fine-Grained Output Control”, IEEE International Symposium on Circuits and Systems (ISCAS), May. 2021.
U. Lee, D. Jang, W. Jung, and M. Je, “Input-Adaptive and Regulated Multi-Output Power Management Unit for Wireless Power Reception and Distribution in Multi-Unit Implantable Devices”, IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2020.
H. Shin, J. Kim, D. Jang, D. Cho, Y. Jung, H. Cho, U. Lee, C. Kim, S. Ha, and M. Je, “A 0.0046mm2 6.7μW Three-Stage Amplifier Capable of Driving 0.5-to-1.9nF Capacitive Load with >0.68MHz GBW without Compensation Zero”, IEEE Symposium on VLSI Circuits (SOVC), Aug. 2020.
E. Lee, D. Jang, and M. Je, “A Level Shifter for CMRR-Enhanced Biopotential Acquisition Systems with Human-Body-Coupled Floating Supply Domain”, IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Nov. 2019.
T. Lee, J.-H. Park, J.-H. Cha, N. Chou, D. Jang, J.-H. Kim, I.-J. Cho, S.-J. Kim, and M. Je, “A Multimodal Multichannel Neural Activity Readout IC with 0.7μW/Channel Ca2+-Probe-Based Fluorescence Recording and Electrical Recording”, IEEE Symposium on VLSI Circuits (SOVC), Jul. 2019.
H. Jeon, J.-S. Bang, Y. Jung, T. Lee, Y. Jeon, S.-T. Koh, J. choi, D. Jang, S. Hong, and M. Je, “A 3.9μW, 81.3dB SNDR, DC-coupled, Time-based Neural Recording IC with Degeneration R-DAC for Bidirectional Neural Interface in 180nm CMOS”, IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2018.
D. Jang, T. Lee, H. Jeon, S. Koh, J. Choi, J. Lee, and M. Je, “16-Channel High-CMRR Neural-Recording Amplifiers Using Common-Made-Tracking Power Supply Rails”, IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), Nov. 2018.
T. Lee, D. Jang, Y. Jung, H. Jeon, S. Hong, S. Han, J.-U. Chu, J. Lee, and M. Je, “A neural recording amplifier based on adaptive SNR optimization technique for long-term implantation”, IEEE Biomedical Circuits and Systems Conference (BioCAS), Oct. 2017.
